Plot
Adelie BLE direction latency
Checks whether BLE transport latency is symmetric in the two directions.
Project records
Images, videos, 3D models, plots and documents for the floating behavioural platform.
Back to overviewPlot
Checks whether BLE transport latency is symmetric in the two directions.
Plot
Shows the error observed when the current clock model predicts the next synchronisation point.
Plot
Shows how accurately the rolling affine model represents Adelie and Korora time.
Plot
Tracks drift in the host clock-rate estimate used by the synchronisation model.
Plot
Measures the transport portion of each Adelie-to-Korora clock exchange.
Plot
Shows where time is spent as commands travel through BLE, Korora, I²C and Fairy processing.
Plot
Measures complete command-response latency as observed by Adelie.
Plot
Distinguishes a stopped or reset device clock from delayed BLE delivery.
Plot
Separates Korora processing from BLE transport latency during clock exchange.
Plot
Breaks command latency into the stages observed by Adelie on the host.
Plot
Measures routine BLE clock-exchange latency between Adelie and Korora.
Plot
Shows the complete latency distribution, including tails, for each command type.
Plot
Measures end-to-end latency for non-clock experiment commands.
Plot
Uses counter deltas to expose bursts without misleading cumulative totals.
Plot
Shows cross-device event alignment against the Korora reference timeline.
Plot
Compares event timing bias and spread using sample count, median, absolute P95 and absolute maximum.
Plot
Compares the number of application events reported by each device.
Plot
Shows when application events occurred and which device reported them.
Plot
Shows how strongly each accepted synchronisation observation changes the model.
Plot
Summarises prediction bias and tail error for Fairy clock model.
Plot
Compares measured interval-rate error with the firmware clock-rate estimate.
Plot
Tests whether unstable clock intervals degrade synchronisation model quality.
Plot
Shows clock-model availability and reset periods throughout the recording.
Plot
Shows how long event records take to arrive after capture.
Plot
Tracks converted external-event timing error against the Korora reference.
Plot
Summarises event timing bias, spread and tail error for Fairy.
Plot
Provides a diagnostic view of the timing offset seen when an event record arrives.
Plot
Measures how long synchronisation observations take to reach the analysis path.
Plot
Checks the cadence and continuity of synchronisation observations.
Plot
Shows how strongly each accepted synchronisation observation changes the model.
Plot
Tests whether delayed event delivery is associated with timestamp conversion error.
Plot
Shows when external event timestamps are synchronized and when conversion is unavailable.
Plot
Compares firmware fit quality against the independent analysis model.
Plot
Summarises prediction bias and tail error for Galapagos clock model.
Plot
Compares measured interval-rate error with the firmware clock-rate estimate.
Plot
Tests whether unstable clock intervals degrade synchronisation model quality.
Plot
Tracks short-term prediction accuracy and model-reset effects.
Plot
Shows clock-model availability and reset periods throughout the recording.
Plot
Tests whether delayed event delivery is associated with timestamp conversion error.
Plot
Shows when external event timestamps are synchronized and when conversion is unavailable.
Plot
Shows how long event records take to arrive after capture.
Plot
Tracks converted external-event timing error against the Korora reference.
Plot
Summarises event timing bias, spread and tail error for Galapagos.
Plot
Provides a diagnostic view of the timing offset seen when an event record arrives.
Plot
Measures how long synchronisation observations take to reach the analysis path.
Plot
Checks the cadence and continuity of synchronisation observations.
Plot
Provides the complete host-side view of BLE performance and congestion.
Plot
Checks the cadence and stability of the reference events used for cross-device alignment.
Plot
Tracks wireless signal strength and helps distinguish radio degradation from software congestion.
Plot
Highlights the worst observed record-delivery interruption for every device.
Plot
Shows both when record silences occur and how their durations are distributed.
Plot
Compares record cadence across devices and Fairy record categories.
Plot
Shows when each clock model has enough observations and whether it is acquiring or tracking.
Plot
Examines the raw timing pairs used to update each device clock model.
Plot
Summarises the centre, spread and tails of one-step clock prediction errors.
Plot
Compares immediate clock predictions with the residual error of the rolling fit.
Plot
Tracks clock-model fit quality and clock-rate error throughout the recording.
Plot
Compares synchronisation accuracy and rate error across devices.
Plot
Measures alignment between scheduled Galapagos TTL pulses and Korora acquisition.
Plot
Checks that TTL requests reach every pipeline stage and quantifies generation and capture error.
Plot
Shows whether TTL requests complete every stage of the scheduling and acquisition path.
Plot
Summarises completed TTL end-to-end timing error using median, absolute P95 and absolute maximum.
Plot
Validates the internal consistency of generation, acquisition and total-error fields.
Plot
Compares relationships between recorded validation metrics to identify coupled timing and delivery behaviours.
Image
Korora and the reward-port controllers move with the floating platform. BLE connects the untethered platform to behavioural software and the stationary Galapagos timing interface, while UART over RS485 connects devices within the platform.
Image
A reward-port event is timestamped locally, transported to Korora and translated onto the shared experimental timeline using the current affine clock model.
Image
Front view showing the visual cue, speaker, light gate and reward outlet used for cue presentation, snout-entry detection and liquid delivery.
Image
Rear view showing the custom STM32 control board, audio circuitry, valve driver and platform power and communication connectors.
Image
Bench prototype containing the Korora mobile hub, Fairy reward-port controllers, Galapagos timing interface and host control software.
3D model
Interactive GLB model of the full reward-port assembly used for visual inspection of the prototype geometry.
3D model
Interactive GLB model of the reward-port control PCB used to inspect board layout and connector placement.
Image
Shared electrical pulses are captured by independently clocked devices and compared after translation onto the Korora timeline.
Image
A TTL is scheduled through Korora and Galapagos, generated physically and captured to compare requested and measured execution times.
Image
Continuous sessions monitor event capture, TTL generation, synchronisation quality, record delivery and node health.
Video
Bench demonstration of programmable audio playback through a Fairy reward-port controller.
Video
Second bench demonstration of programmable audio playback through a Fairy reward-port controller.