Project records

Media archive

Images, videos, 3D models, plots and documents for the floating behavioural platform.

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Type

One-step clock-model prediction error over time on Adelie.

Plot

Adelie clock prediction error

Shows the error observed when the current clock model predicts the next synchronisation point.

  • adelie
  • clock
  • prediction
Rolling RMS fit error of the Adelie clock model.

Plot

Adelie clock model fit

Shows how accurately the rolling affine model represents Adelie and Korora time.

  • adelie
  • clock
  • synchronisation
Fairy: firmware and independently recomputed clock-model RMS error over time.

Plot

Fairy · Clock model fit

Compares firmware fit quality against the independent analysis model.

  • fairy
  • synchronisation
  • clock
  • model
BLE RSSI measurements over time grouped by logical node.

Plot

BLE signal strength by node

Tracks wireless signal strength and helps distinguish radio degradation from software congestion.

  • ble
  • rssi
  • connectivity
Bar chart of the longest periods without a record from each node.

Plot

Longest record silences

Highlights the worst observed record-delivery interruption for every device.

  • records
  • gaps
  • reliability
Three-panel timeline of output queue depth, dropped records and transport errors.

Plot

Node transport health

Tracks queue pressure, record loss and transport faults for each device.

  • health
  • records
  • transport
Received record rate over time for each logical node.

Plot

Record rate by node

Shows the cadence of records reaching Adelie from every device.

  • records
  • throughput
  • nodes
Two-panel timeline of model population and synchronisation tracking state.

Plot

Synchronisation model state

Shows when each clock model has enough observations and whether it is acquiring or tracking.

  • synchronisation
  • clock
  • state
Timeline and distribution of Galapagos TTL timing error.

Plot

TTL alignment detail

Measures alignment between scheduled Galapagos TTL pulses and Korora acquisition.

  • ttl
  • timing
  • galapagos
Counts of completed, timed-out and incomplete scheduled TTL pulses.

Plot

Scheduled TTL pulse outcomes

Shows whether TTL requests complete every stage of the scheduling and acquisition path.

  • ttl
  • reliability
  • outcomes
Correlation matrix comparing timing-verification metrics across validation records.

Plot

Verification metric correlations

Compares relationships between recorded validation metrics to identify coupled timing and delivery behaviours.

  • validation
  • timing
  • diagnostics
Diagram separating the floating-platform communication network from stationary behavioural-control and DAQ equipment.

Image

Physical communication architecture

Korora and the reward-port controllers move with the floating platform. BLE connects the untethered platform to behavioural software and the stationary Galapagos timing interface, while UART over RS485 connects devices within the platform.

  • system
  • communication
  • korora
  • fairy
  • galapagos
  • ble
  • rs485
Diagram showing a reward-port event timestamped locally, transported through Korora and translated onto a shared timeline.

Image

From local detection to a common timeline

A reward-port event is timestamped locally, transported to Korora and translated onto the shared experimental timeline using the current affine clock model.

  • system
  • timing
  • events
  • synchronisation
  • korora
  • fairy
Front view of a reward port showing cue, speaker, light gate and liquid-delivery outlet.

Image

Reward-port front assembly

Front view showing the visual cue, speaker, light gate and reward outlet used for cue presentation, snout-entry detection and liquid delivery.

  • system
  • reward-port
  • fairy
  • hardware
  • prototype
Rear view of a reward-port controller with STM32 control electronics and connectors.

Image

Reward-port control electronics

Rear view showing the custom STM32 control board, audio circuitry, valve driver and platform power and communication connectors.

  • system
  • reward-port
  • fairy
  • electronics
  • prototype
Bench prototype with the Korora hub, Fairy reward-port controllers, Galapagos timing interface and host control software.

Image

Integrated breadboard prototype

Bench prototype containing the Korora mobile hub, Fairy reward-port controllers, Galapagos timing interface and host control software.

  • system
  • prototype
  • korora
  • fairy
  • galapagos
Interactive 3D model of the complete Fairy reward-port assembly.

3D model

Full reward-port 3D model

Interactive GLB model of the full reward-port assembly used for visual inspection of the prototype geometry.

  • system
  • reward-port
  • fairy
  • model
  • hardware
Interactive 3D model of the Fairy reward-port control PCB.

3D model

Reward-port PCB 3D model

Interactive GLB model of the reward-port control PCB used to inspect board layout and connector placement.

  • system
  • reward-port
  • fairy
  • model
  • pcb
  • electronics
Validation diagram showing shared electrical pulses captured by independently clocked devices.

Image

External event validation method

Shared electrical pulses are captured by independently clocked devices and compared after translation onto the Korora timeline.

  • validation
  • events
  • timing
  • method
Validation diagram showing scheduled Galapagos TTL pulses captured by an external measurement system.

Image

Physical output validation method

A TTL is scheduled through Korora and Galapagos, generated physically and captured to compare requested and measured execution times.

  • validation
  • ttl
  • timing
  • method
  • galapagos
Validation diagram showing continuous logging of synchronisation, delivery and node-health records over time.

Image

Long-duration stability method

Continuous sessions monitor event capture, TTL generation, synchronisation quality, record delivery and node health.

  • validation
  • stability
  • timing
  • health
  • method